Reset System
7 min
reset system the pic18f2455/2550/4455/4550 devices support multiple reset conditions to ensure reliable startup and fault recovery understanding the reset system is important for designing stable embedded applications types of reset the following table summarizes all reset events recognized by the device reset type description power on reset (por) occurs when power is applied and vdd rises to the operating range mclr reset (normal) external reset triggered through the mclr pin during operation mclr reset (power managed) external reset during sleep or idle modes wdt reset reset caused by a watchdog timer time‑out during code execution brown out reset (bor) occurs when vdd drops below the bor threshold reset instruction software triggered reset stack full reset triggered by hardware stack overflow stack underflow reset triggered by hardware stack underflow rcon register the rcon register monitors and controls reset states it contains status flags that indicate the reset source and includes control bits for interrupt priority and bor functionality rcon bits summary bit name meaning notes 7 ipen interrupt priority enable enables the multi level interrupt system 6 sboren software brown out enable controls bor operation based on configuration settings 4 ri reset instruction flag indicates execution of the reset instruction 3 to watchdog time out flag cleared when a wdt time‑out occurs 2 pd power down flag set on power up or clrwdt and cleared on sleep 1 por power on reset flag indicates por detection 0 bor brown out reset flag indicates a bor event reset operation overview the reset system includes several internal mechanisms power on reset (por) triggered by a vdd rise and coordinated with the pwrt (power up timer) brown out reset (bor) triggered when voltage falls below the safe operating threshold oscillator start up timer (ost) ensures oscillator stability before program execution watchdog timer reset (wdt) initiated when software fails to service the wdt within the required period a simplified block diagram in the datasheet illustrates the internal relationships among mclr, pwrt, ost, intrc, bor, and related circuits reset behavior reset status flags remain set until cleared by firmware a typical reset handling sequence is read the rcon register after startup determine the reset source based on the status flags clear the relevant bits for subsequent reset detection common combinations por = 0, bor = 1 → power on reset detected por = 1, bor = 0 → brown out reset detected to = 0 → wdt time‑out detected notes firmware should set por after detecting a power on reset to allow future por event detection bor is considered to have occurred when bor = 0 and por = 1 reset flags may require manual clearing by firmware this document provides an overview of the reset subsystem and associated diagnostic behavior for the pic18f2455/2550/4455/4550 family
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