Power-Managed Modes

power managed modes the pic18f2455/2550/4455/4550 devices provide seven operating modes for efficient power management these modes offer flexible options for conserving power in battery‑powered and energy‑sensitive applications the power‑managed modes are grouped into three categories run modes idle modes sleep mode these categories determine which portions of the device are clocked and the operating frequency in use run and idle modes may use any of the three available clock sources primary, secondary, or the internal oscillator block sleep mode operates without a clock source the pic18 family includes advanced power‑saving capabilities such as clock switching through the timer1 oscillator and a full sleep mode in which clocks are disabled selecting power managed modes selecting a mode requires two configuration decisions whether the cpu should be clocked which clock source should be used the idlen bit (osccon<7>) controls cpu clocking the scs1 \ scs0 bits (osccon<1 0 >) select the clock source power managed modes table (summary) mode selection depends on the cpu clock and selected oscillator mode clock source cpu clocked peripherals clocked pri idle primary no yes sec idle timer1 oscillator no yes rc idle internal oscillator no yes clock sources the scs1\ scs0 bits determine the clock source primary clock (fosc configuration bits) secondary clock (timer1 oscillator) internal oscillator block entering power managed modes power‑managed modes are selected by updating the osccon register changing scs1\ scs0 switches clock sources immediately if the selected source is already running idle or sleep modes are entered by executing the sleep instruction, depending on the value of idlen clock transitions and status indicators clock transition timing two cycles of the previous clock three to four cycles of the new clock status bits osts – primary clock stable iofs – internal oscillator stable t1run – timer1 oscillator running multiple sleep commands when executing consecutive sleep instructions, a delay of at least one instruction cycle (tcy) is required example sleep nop ; wait 1 tcy sleep run modes pri run mode default full‑power operating mode osts set iofs may also be set sec run mode cpu and peripherals clocked from timer1 entered with scs1\ scs0 = 01 primary oscillator shuts down t1run set and osts cleared note the timer1 oscillator must be running before entering sec run mode sleep mode sleep mode operates in the same manner as legacy pic sleep modes entered by clearing idlen and executing sleep shuts down the selected oscillator clears all clock source status bits if wdt is enabled, the intrc source continues operating if the timer1 oscillator is enabled, it also remains active upon wake‑up through an interrupt, reset, or wdt time‑out the device resumes operation only after the selected clock source becomes ready if fail‑safe clock monitor or two‑speed start‑up is enabled, the internal oscillator may temporarily provide the execution clock idle modes idle modes suspend cpu execution while allowing peripherals to remain active pri idle mode primary clock remains active provides fast wake‑up response sec idle mode peripherals clocked from timer1 t1run set and osts cleared rc idle mode peripherals clocked from the internal oscillator intosc output stabilizes according to the ircf bit settings exiting idle and sleep modes exit conditions include interrupts, wdt time‑outs, and reset events exit behavior summary exit source resulting action notes interrupt wake to run mode requires tcsd delay wdt time out wake or reset depends on current mode reset ost or internal oscillator start clock source dependent after exit, code execution resumes following the required delay period, including tcsd or oscillator start‑up timing where applicable this document summarizes the power‑managed operating modes and related control behavior for the pic18f2455/2550/4455/4550 device family