---
title: Reset System
slug: docs-preview/reset-system
docTags: 
createdAt: 2026-06-29T07:35:54.844Z
---

# Reset System

The PIC18F2455/2550/4455/4550 devices support multiple reset conditions to ensure reliable startup and fault recovery. Understanding the reset system is important for designing stable embedded applications.

## Types of Reset

The following table summarizes all reset events recognized by the device:

***

| Reset Type                 | Description                                                        |
| -------------------------- | ------------------------------------------------------------------ |
| Power-on Reset (POR)       | Occurs when power is applied and VDD rises to the operating range. |
| MCLR Reset (Normal)        | External reset triggered through the MCLR pin during operation.    |
| MCLR Reset (Power-managed) | External reset during Sleep or Idle modes.                         |
| WDT Reset                  | Reset caused by a Watchdog Timer time‑out during code execution.   |
| Brown-out Reset (BOR)      | Occurs when VDD drops below the BOR threshold.                     |
| RESET Instruction          | Software-triggered reset.                                          |
| Stack Full Reset           | Triggered by hardware stack overflow.                              |
| Stack Underflow Reset      | Triggered by hardware stack underflow.                             |

***

## RCON Register

The **RCON** register monitors and controls reset states. It contains status flags that indicate the reset source and includes control bits for interrupt priority and BOR functionality.

### RCON Bits Summary

***

| Bit | Name   | Meaning                   | Notes                                                   |
| --- | ------ | ------------------------- | ------------------------------------------------------- |
| 7   | IPEN   | Interrupt Priority Enable | Enables the multi-level interrupt system.               |
| 6   | SBOREN | Software Brown-out Enable | Controls BOR operation based on configuration settings. |
| 4   | RI     | RESET Instruction Flag    | Indicates execution of the RESET instruction.           |
| 3   | TO     | Watchdog Time-out Flag    | Cleared when a WDT time‑out occurs.                     |
| 2   | PD     | Power-Down Flag           | Set on power-up or CLRWDT and cleared on SLEEP.         |
| 1   | POR    | Power-on Reset Flag       | Indicates POR detection.                                |
| 0   | BOR    | Brown-out Reset Flag      | Indicates a BOR event.                                  |

***

## Reset Operation Overview

The reset system includes several internal mechanisms:

- **Power-on Reset (POR):** Triggered by a VDD rise and coordinated with the PWRT (Power-up Timer).
- **Brown-out Reset (BOR):** Triggered when voltage falls below the safe operating threshold.
- **Oscillator Start-up Timer (OST):** Ensures oscillator stability before program execution.
- **Watchdog Timer Reset (WDT):** Initiated when software fails to service the WDT within the required period.

A simplified block diagram in the datasheet illustrates the internal relationships among MCLR, PWRT, OST, INTRC, BOR, and related circuits.

## Reset Behavior

Reset status flags remain set until cleared by firmware. A typical reset handling sequence is:

1. Read the **RCON** register after startup.
2. Determine the reset source based on the status flags.
3. Clear the relevant bits for subsequent reset detection.

Common combinations:

- POR = 0, BOR = 1 → Power-on Reset detected.
- POR = 1, BOR = 0 → Brown-out Reset detected.
- TO = 0 → WDT time‑out detected.

## Notes

- Firmware should set `POR` after detecting a Power-on Reset to allow future POR event detection.
- BOR is considered to have occurred when **BOR = 0** and **POR = 1**.
- Reset flags may require manual clearing by firmware.

This document provides an overview of the reset subsystem and associated diagnostic behavior for the PIC18F2455/2550/4455/4550 family.