---
title: Power-Managed Modes
slug: docs-preview/power-managed-modes
docTags: uvyLbgOHV4hEy25Qe4xRR
createdAt: 2026-06-29T07:32:51.447Z
---

# Power-Managed Modes

The PIC18F2455/2550/4455/4550 devices provide seven operating modes for efficient power management. These modes offer flexible options for conserving power in battery‑powered and energy‑sensitive applications.

The power‑managed modes are grouped into three categories:

- Run modes
- Idle modes
- Sleep mode

These categories determine which portions of the device are clocked and the operating frequency in use. Run and Idle modes may use any of the three available clock sources: primary, secondary, or the internal oscillator block. Sleep mode operates without a clock source.

The PIC18 family includes advanced power‑saving capabilities such as clock switching through the Timer1 oscillator and a full Sleep mode in which clocks are disabled.

## Selecting Power-Managed Modes

Selecting a mode requires two configuration decisions:

- Whether the CPU should be clocked
- Which clock source should be used

The **IDLEN bit (OSCCON\<7>)** controls CPU clocking.
The **SCS1**:SCS&#x30;**&#x20;bits (OSCCON\<1**:&#x30;**>)** select the clock source.

## Power-Managed Modes Table (Summary)

Mode selection depends on the CPU clock and selected oscillator.

***

| Mode      | Clock Source        | CPU Clocked | Peripherals Clocked |
| --------- | ------------------- | ----------- | ------------------- |
| PRI\_IDLE | Primary             | No          | Yes                 |
| SEC\_IDLE | Timer1 Oscillator   | No          | Yes                 |
| RC\_IDLE  | Internal Oscillator | No          | Yes                 |

***

## Clock Sources

The `SCS1:SCS0` bits determine the clock source:

- **Primary clock** (FOSC configuration bits)
- **Secondary clock** (Timer1 oscillator)
- **Internal oscillator block**

## Entering Power-Managed Modes

Power‑managed modes are selected by updating the **OSCCON** register. Changing `SCS1:SCS0` switches clock sources immediately if the selected source is already running.

Idle or Sleep modes are entered by executing the **SLEEP** instruction, depending on the value of `IDLEN`.

## Clock Transitions and Status Indicators

Clock transition timing:

- Two cycles of the previous clock
- Three to four cycles of the new clock

Status bits:

- **OSTS** – Primary clock stable
- **IOFS** – Internal oscillator stable
- **T1RUN** – Timer1 oscillator running

## Multiple Sleep Commands

When executing consecutive SLEEP instructions, a delay of at least one instruction cycle (TCY) is required.

Example:

```assembly
SLEEP
NOP        ; wait 1 TCY
SLEEP
```

## Run Modes

### PRI\_RUN Mode

- Default full‑power operating mode
- `OSTS` set
- `IOFS` may also be set

### SEC\_RUN Mode

- CPU and peripherals clocked from Timer1
- Entered with `SCS1:SCS0 = 01`
- Primary oscillator shuts down
- `T1RUN` set and `OSTS` cleared

:::BlockQuote
**Note:** The Timer1 oscillator must be running before entering SEC\_RUN mode.
:::

***

# Sleep Mode

Sleep mode operates in the same manner as legacy PIC Sleep modes.

- Entered by clearing `IDLEN` and executing **SLEEP**.
- Shuts down the selected oscillator.
- Clears all clock source status bits.

If WDT is enabled, the INTRC source continues operating. If the Timer1 oscillator is enabled, it also remains active.

Upon wake‑up through an interrupt, Reset, or WDT time‑out:

- The device resumes operation only after the selected clock source becomes ready.
- If Fail‑Safe Clock Monitor or Two‑Speed Start‑up is enabled, the internal oscillator may temporarily provide the execution clock.

***

# Idle Modes

Idle modes suspend CPU execution while allowing peripherals to remain active.

### PRI\_IDLE Mode

- Primary clock remains active.
- Provides fast wake‑up response.

### SEC\_IDLE Mode

- Peripherals clocked from Timer1.
- `T1RUN` set and `OSTS` cleared.

### RC\_IDLE Mode

- Peripherals clocked from the internal oscillator.
- INTOSC output stabilizes according to the IRCF bit settings.

***

# Exiting Idle and Sleep Modes

Exit conditions include interrupts, WDT time‑outs, and Reset events.

### Exit Behavior Summary

***

| Exit Source  | Resulting Action                 | Notes                   |
| ------------ | -------------------------------- | ----------------------- |
| Interrupt    | Wake to Run Mode                 | Requires TCSD delay     |
| WDT Time-Out | Wake or Reset                    | Depends on current mode |
| Reset        | OST or internal oscillator start | Clock source dependent  |

***

After exit, code execution resumes following the required delay period, including TCSD or oscillator start‑up timing where applicable.

This document summarizes the power‑managed operating modes and related control behavior for the PIC18F2455/2550/4455/4550 device family.